مبدل هاي آنالوگ به ديجيتال سريع با ولتاژ تغذيه و توان پايين امروزه از عناصر كليدي سيستمهاي پردازشي و مخابراتي به شمار مي روند. كاربرد روز افزون دستگاههاي الكترونيكي كه با باتري كار مي كنند، مسئله ولتاژ تغذيه و بخصوص توان مصرفي را از اهميت ويژه اي برخوردار ساخته است.

The scaling of CMOS technologies has increased the performance of general
purpose processors and DSPs. However, analog circuits designed in the same process
have not been able to utilize the scaling to the same extent, suffering from reduced
voltage headroom and reduced analog gain. Integration of the system components on
the same die means that the analog-to-digital converters (ADCs) needs to be
implemented in the newest technologies in order to utilize the digital capabilities at
these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there
is a need to both understand the physical limitations as well as to develop new
architectures and circuits that take full advantage of the potential that process has to
offer.
As the technology scales to smaller feature sizes, the possible sample-rate of ADCs
can be increased. This thesis explores the design of high-speed ADCs and investigates
architectural and circuit concepts that address the problems associated with lower
supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is
investigated and lower bounds, as set by both thermal noise and minimum feature sizes
are formulated. Utilizing the increasing digital performance, low-accuracy analog
components can be used, assisted by digital correction or calibration, which leads to a
reduction in power dissipation. Through the aid of new techniques and concepts, the
power dissipation of low-to-medium resolution ADCs benefit from going to more
modern CMOS processes, which is supported by both theory and published results